The present invention relates generally to semiconductor devices, and more particularly, to a structure and method for forming a fin field effect transistor (finFET) device having a low external resistance.
FinFET devices have been proposed to enable continued scaling of complementary metal oxide semiconductor (CMOS) technology at under 20 nm gate lengths. As the dimensions within finFET devices become ever smaller, undesirable parasitic effects such as capacitance from a gate to a source-drain and parasitic resistance in the source-drain may severely impact the performance of finFET devices.